RD11/EAST introduction

EAST-RD11 Introduction

To handle its extraordinary data rates, the future hadronic collider LHC will require novel detectors, both highly time-sensitive and selective. A one-in-a-million or more reduction in event rate between bunch crossing and recording has to be implemented in real time; new and unfamiliar technologies will be needed to reliably extract the physics content from the original collision rate of 100 MHz. The selection is called triggering, and it will be implemented in several levels, each reducing the data rate by some factor, with increasingly complex algorithms.

The main purpose of the EAST (or RD11) project has been to explore implementations of architectures to be used after a first-level trigger. An input frequency of 100 kHz is generally accepted to be realistic for this 'second level', as shown by physics and detector simulation done for the proposed LHC experiments. The algorithms needed to exploit detector capabilities require fine-grain data, at least for some critical detectors. Their execution time in today's fastest high-level processors is tens of milliseconds per event; further, at the required frequency, the necessary data can not be collected readily in standard processors by commercial communication elements. Parallelism and clever communication hence are needed to cope with the problem.

EAST has developed the quite fundamental Region-of-Interest (RoI) concept for level- 2 triggering, at least at high luminosity. RoI-s are spatially limited areas in the detector in which the level-1 trigger has identified candidates for phenomena to be triggered on (electrons, photons, muons, hadrons, jets). EAST has also decomposed the algorithms functionallyinto three phases:

The three phases can be implemented in different hardware, and run in parallel pipelined mode, if required. Demonstrated implementations vary from fast electronics- like processing in programmable gate arrays (FPGA-s) to farms composed of commercial processing and networking components (which compensate the comparativeley slow performance by having large numbers of components working simultaneously on many different events).

Detailed activity reports can be seen from EAST's status reports (1992, 1993, 1994, 1995) and other publications. The following key results obtained in EAST over 1991-95 are on a separate page

Short rundown of results achieved in EAST

Algorithm definition and test data

Much work was invested in an acceptable problem definition and the provision of simulated test data.

Benchmarking feature extraction algorithms

The most critical algorithms (closest to the detector) were benchmarked on a variety of architectural possibilities, and published results exist. Conclusion: SIMD architectures (many identical processors working synchronously on different data, executing the same instructions) are not a suitable solution, pipelined devices can keep up with the data rates of L2. The execution of feature extraction algorithms in high-level processors typically takes milliseconds per RoI and detector; in other words, several thousands of processors will be needed in a L2 farm, with today's best available processors.

Build hardware emulators, standardize transmission

For testing the more promising implementations at full speed, a programmable data source ('detector in a crate') was defined, and used under the name of SLATE both for hardware tests and for demonstration purposes (SLATE modules have been available since 1992).

Implement data-driven processors for feature extraction

The most critical parts of the trigger, due to combined bandwidth and frequency requirements, RoI collection and local feature extraction, were implemented in a data- driven variety, using as test bed SLATE modules and an LHC detector prototype, RD6's transition radiation detector sectors.

Neural networks

EAST has explored several possibilities of using algorithm formulations in terms of artificial neural networks (ANN-s). Some success was reported in feature extraction for clustering algorithms, but the need for non-ANN pre-processing and the lack of breakthroughs in commercially available ANN processors have left this work without a proposal to implement a practical solution. As a method of optimising algorithms in the global decision, however, ANN-based formulations have demonstrated superiority.

Farms and HPCN systems

Level-2 problems were mapped onto some of today's commercial switches with standard software of driving communications, and onto high-speed RISC processors and DSP-s. Solutions based on TMS320C40 processors with DS-link switches, or on SCI and Digital's Alpha processors are under investigation (jointly with Atlas and RD24). Some extrapolations to systems of the HPCN category (High-Performance Computers and Networks) were attempted (CS-2, SP-2, Convex).

System specification (VDM++)

EAST has been an application partner in exploring the practical use of formal specification of mixed hardware/software systems, in a project that is sponsored by Esprit II (AFRODITE). The development partners foresee marketing a commercial language (VDM++) and supporting development packages based on Verilog's OMT, and the Utrecht/CERN partners have used the language for successfully specifying the currently investigated level-2 implementations.

An overview of the LHC second level trigger domain, in colour or black and white

RD11 November 14, 1994